Design for Test Engineer - Central DFT (111842)

工作内容

What You Do At AMD Changes Everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

The Successful Candidate Will Be Responsible Of

• Working with a multi-discipline and international team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture, tool and methodology initiatives
• Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows
• Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and closure including defining constraints
• Writing and maintain DFT documentation and specifications
• Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design
• Performing scan insertion, ATPG verification and test pattern generation
• Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis
  

Candidate Must Have

REQUIRED EXPERIENCE:

• Minimum B.Sc in Electrical or Computer Engineering (or equivalent)
• Minimum 5 years of ASIC design experience
• Demonstrated technical leadership and works well with cross-functional teams
• Excellent communication and interpersonal skills
• Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design
• Understanding various technologies that must work with DFT/DFD technology such as CPU’s, Graphics engines, memory and I/O controllers, etc.
• Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential
• Working knowledge and experience in verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
• Experience in solving logic design or timing issues with integration, synthesis and PD teams
• Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming
• Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis
• Knowledge of ATE and digital IC manufacturing test is a plus
  

Requisition Number:111842

Country:Canada Province:Ontario City:Markham

Job Function:Design

AMD is an inclusive employer dedicated to building a diverse workforce. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective provincial human rights codes throughout all stages of the recruitment and selection process. Any applicant who requires accommodation should contact AskHR@amd.com .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services.