Senior Digital Verification Manager

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Directs and guides the activities of a Digital Verification team responsible for test and verification Synopsys Designware High Bandwidth Memory (HBM) PHY IP. The candidate will be tasked with leading a team of engineers responsible for verifying all aspects of the Digital elements of the HBM PHY product offering.

Background and experience in the following areas are essential to the success:

• Team Leadership – incumbent will lead a team of engineers
• Defining, designing and implementing verification systems.
• Defining, designing and implementing infrastructure and methods to support the. planning, tracking and management of verification projects and programs.
• Close collaboration with architecture team to verify the completeness and correctness of definition and requirements – incumbent will ensure design implementation can be verified to meet all quality and functional requirements as specified.
• Close collaboration with digital design teams to verify the completeness and correctness of implementation – incumbent will ensure design implementation meets all quality and functional requirements as specified.
• Close collaboration with internal physical implementation teams implementing the digital systems – incumbent will help to ensure consumers of the Digital portion of the HBM PHY IP are enabled to achieve successful physical implementation.
• Close collaboration with sales and marketing teams during customer pre-sales and sales process – incumbent may be required to work with and support customer relationships and sales activities.
• Close collaboration with Applications Engineering teams supporting internal and external customers – incumbent may be required to work with and support customer technical support activities.

Requires strong hands-on SOC verification experience and knowledge of all facets of the digital verification process.

Advanced experience with SystemVerilog and UVM is highly desirable.

Strong organization and communications skills are very important.

Previous experience managing or leading verification teams is a strong asset.

Experience with mixed signal circuits and integration with digital systems is an asset.

Experience with gate level simulation is an asset.

Previous experience with DDR memory technology is beneficial and is ideally coupled with a diverse background across digital SOC verification areas.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.